clist14.html

Cheryl's List #14 - Septmeber 10, 1998

http://www.watsonwalker.com/archives.html

1. Nifty Updates to Our Web Page:
Link of the Week and Getting to Goal Mode

We’ve just added two items to our home page. The first is a LINK OF THE WEEK. Each week I’ll write about an interesting OS/390 site. The second new item is an article called “Getting to Goal Mode – Step by Step”; it’s a short list of the mechanics of getting goal mode implemented in a test environment (e.g. how to build the couple data sets).

2. Latest Processor News

They’re getting smaller, faster, and cheaper – mainframes are turning the industry around. Once thought dead, mainframes are now a success story!

As we mentioned in earlier Cheryl’s Lists, IBM announced a 125 MIPS CMOS processor (G5 series) in May of this year. HDS followed shortly afterward by indicating they would provide comparable machines with their Pilot 8 series. And Amdahl announced their upcoming Millennium 800 series in June with close to 1000 MIPS. Then IBM announced on July 28th that their previously announced G5 series was faster than anticipated (up to 1040 MIPS for a 10-way and sporting a 150 MIPS uni). HDS weighed in saying that they would be meeting that performance too. (After all, they use the same chips, even though some of the other architecture differs.) And just last week, IBM has again announced a boost in capacity. Well, they didn’t really announce it, but they posted their final LSPR ratings that show the top-end turbo machine at a rocketing 1065 MIPS (in my evaluation)! Amdahl, not one to shy away from the party, tells us the Millennium 800 series exceeds the capacity of IBM's G5 (>1065 MIPS) and will begin shipping before the end of this year.

Would you have believed this four years ago? Then the top-end machines were IBM’s 9021-9X2 10-way at 465 MIPS capacity, HDS’s GX8824 8-way machine at 389 MIPS, and Amdahl’s 5995-12670 12-way at 530 MIPS. CMOS arrived on the scene in April of 1994 and in four years, the CMOS processors have jumped from a 62 MIPS 6-way (with only a 14 MIPS uni) to a 1065 MIPS 10-way (with a 150 MIPS uni). That’s more than a 10-fold jump in speed for CMOS (and a 17-fold jump in capacity) in four years. Pretty impressive! All of the vendors are showing significant advances in speed and capacity every year. It’s an exciting time to be in the mainframe world.

We’ve updated our CPU Chart based on the latest LSPR ratings, and it now includes MIPS by workload for the new series. Subscribers to Cheryl Watson’s TUNING Letter may call or send us an email with their company name and address in order to receive the updated MIPS. Rather than request a return email, we’d recommend that you send your fax number so we can send you MIPS by workload (a copy of the CPU Chart page). The updates will be mailed in a new CPU Chart in a few weeks.

Listed below are the new or changed Processor groups, MSUs, and version codes.

IBM Model Proc CPUs Grp MSUs Ver

9672-RB6 2 60 28 8E (was 29 MSUs)

9672-RC6 3 80 55 8D (was 53 MSUs)

9672-RD6 4 80 71 8C (was IMLC, 66 MSUs)

9672-RX6 10 IMLC 156 8A (was 153 MSUs)

9672-Y76 7 IMLC 146 4D (new)

9672-YX6 10 IMLC 186 8B (was 183 MSUs)

3. Updates to Cheryl Watson’s TUNING Letter

In our 1998, No. 2 issue on page 6, we mentioned a SAS zap, Z609E562, needed if you are running OS/390 R2. It should have been Z609E526 instead. Howard Glastetter from Weyerhaeuser was kind enough to send us an email with the correction.

Bob Shannon’s article on the LOADxx parmlib member in our TUNING Letter, 1998, No. 3, was well received, but here are a few updates. Lou D'Agnolo from Innovation Data Processing pointed out a statement on page 36 that’s incorrect. The statement was: If ‘*mcat*’ is coded only the master catalog will be searched. As Lou points out, the manual states that if ‘*mcat*’ is specified, IPL processing will attempt to locate the specified data set on the master catalog volume. Lou found out the hard way when he couldn’t IPL an OS/390 2.5 system.

Paul Kaufman of GTE Data Services pointed out another item in the same article. The article stated on page 37 that if the SYSPARM parameter is coded, the response is automatic. As Paul points out, that is not true. The SYSPARM parameter is only used if the prompt for the System Parameters is disabled. If the Load parameters are set to prompt for System Paramers, the SYSPARM parameters in LOADxx and/or IEASYMxx are ignored. If the Load parameters are set to disable the prompt for System Parameters and no SYSPARM parameters are specified, the system will not prompt for any. It will use a default of 00. The recommendation to have an alternate LOAD member should instead be to know how to enable the prompt.

For the same article, a statement on page 38 said that the Parmlib Checker “can validate the syntax of parmlib members”. Bruce Christopher from Household International pointed out that syntax is not checked. It was a typo that should have said “symbolics”, that is, it will only check that references to other parmlib members point to members that exist. Also, readers had asked about where to find documentation on Bob’s reference to SYS1.IBM.PARMLIB. It appears to only be documented in the online help facility in the ServerPac dialogue.

In our 1998, No. 3 issue on page 8, we alerted you to WSC Flash 9824 which recommends applying the ADSM 3.1.1.3 maintenance. Unfortunately, David Ehresman from University of Louisville followed IBM’s recommendation and applied the maintenance. David just provided this warning: “Please be aware there is a serious error in this maintenance level for users who are using colocation. We were having backups fail on a daily basis until we dropped back to the 3.1.1.2 server maintenance. The open APAR, which is not expected to have a fix for a couple of months(!) is IX81205.”

4. Request for LE Experiences

I’m busy working on the next newsletter issue that has a focus on Language Environment (LE). I’d love to include as many user experiences as possible, so if you have anything to share, please send it to me within the next week. Some of the things I’ll be discussing are: 1) How much overhead does LE take? 2) Is it better to put LE in the LinkList immediately or wait? 3) Are the levels of LE compatible (if not, what were the problems)? 4) How long does it take for the planning stage of LE? 5) How long does it take to completely implement LE? I’d appreciate any feedback, especially your thoughts on these questions. Please let me know whether I may use your name and company in the newsletter.

That's all for now. Stay tuned!

Cheryl Watson

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